A conventional sensing circuit (also referred to as a sense amplifier) 100 used in semiconductor memories, particularly non-volatile semiconductor memories and, even more particularly, in those memories having a memory cell matrix with the so-called NOR architecture, has the general structure depicted in FIG. 1. The memory, for example a Flash memory, includes a bi-dimensional array 105 (the memory cell matrix, or memory matrix) of matrix memory cells MC, typically MOS transistors having a charge-storage element, e.g., a floating gate, that is adapted to be selectively charged with electric charges (electrons) so as to vary the MOS transistor's threshold voltage. The matrix memory cells are arranged by rows and columns, and are each connected to a respective matrix word line WL and matrix bit line BL,m.
A generic matrix memory cell MC,m is selected, e.g., for reading its content, by selecting the respective word line and bit line, respectively through a word line selector 110 and a bit line selector 115, which are responsive to an address ADD supplied to the memory, e.g., from the outside, such as from an external microcontroller (not shown). The matrix bit line BL,m that contains the one matrix memory cell selected for reading is electrically connected (through the bit line selector 115) to a first circuit branch 120a of the sense amplifier 100; the first circuit branch 120a is thus run through by a matrix memory cell current I,m. The first circuit branch 120a contains a load Lda that is tied to a supply voltage distribution rail VDD that distributes, through the memory IC chip, the supply voltage VDD provided to the IC chip from the outside, and, in series with the load LDa, a bit line voltage regulator 130a. The bit line voltage regulator typically comprises a cascode-connected N-channel MOSFET N11a, which is inserted between the load LDa and the matrix bit line BL,m. The cascode-connected MOSFET N11a is feedback-controlled, by being inserted in a negative feedback network, typically comprising an inverter IN1a, which has its input and output respectively connected to the source and the gate of the cascode-connected MOSFET N11a. 
The sense amplifier 100 comprises at least one second circuit branch 120b, which is intended to be run through by a respective reference current I,r. One second circuit branch is sufficient in the case in which the memory includes bi-level memory cells (i.e., memory cells whose threshold voltage can take either one of two possible values), which are capable of storing one bit each, or also in the case of multi-level memory cells (whose threshold voltage can take more than two values), which are adapted to store more than one bit each, provided that a serial, particularly a serial dichotomic sensing approach, is adopted for sensing the multi-level memory cells. More than one second circuit branch may be necessary in some cases, for example in a case in which the sense amplifier is intended to sense multi-level memory cells, and a parallel sensing approach is adopted. The second circuit branch 120b is typically identical to the first circuit branch 120a, and contains a load Ldb, which is tied to the supply voltage distribution rail VDD, and, in series with the load LDb, a bit line voltage regulator 130b comprising a cascode-connected N-channel MOSFET N11b, which is inserted in a negative feedback network, which comprises an inverter IN1b having its input and output respectively connected to the source and the gate of the MOSFET N11b. The N-channel MOSFET N11b is inserted between the load LDb and a reference bit line BL,r, which contains a reference memory cell MC,r that is structurally identical to the matrix memory cells MC,m, but set in a well-known programming state (more than one such reference memory cell is typically used in the case in which the sense amplifier is intended for sensing multi-level memory cells).
The loads LDa and LDb act as current-to-voltage conversion elements, for respectively converting the matrix memory cell current I,m, and the reference current I,r into respective voltage signals. The loads LDa and LDb can be implemented by resistors, transistors (e.g., P-channel MOSFETs), current loads and the like.
The bit line voltage regulators 130a and 130b regulate the voltage of the matrix bit line BL,m and that of the reference bit line BL,r (and thus the drain potential of the matrix and reference memory cells MC,m and MC,r; for this reason, they are also referred to as drain voltage regulators) to approximately 1V, a value that avoids stressing the memory cells (matrix and reference) and causing spurious “soft-programming” thereof.
Circuit nodes MAT and REF, corresponding to the drains of the MOSFETs N11a and N11b, respectively, are connected to the non-inverting and inverting inputs of a comparator or differential amplifier 125, which is adapted to amplify a voltage difference between these two circuit nodes MAT and REF substantially to a full logic-level voltage.
An output of the differential amplifier 125, which carries the data bit stored in the memory cell, is fed to output data buffers of the memory (not shown) for being made available to the outside of the memory.
In the case in which the memory contains multi-level memory cells and the parallel sensing approach is adopted, as many comparators as the number of second circuit branches are provided, and their outputs are fed to a combinational logic circuit that is capable of extracting the read multi-bit data from the outputs of the various comparators.
In a sensing operation, the selected matrix bit line BL,m is normally pre-charged to a predetermined potential. During this phase, the potential of the selected matrix word line WL to which the selected matrix memory cell MC,m belongs is also raised to a read word line potential, typically the supply voltage VDD, or possibly (when the value of the supply voltage VDD is low) a higher voltage, which is generated internally to the chip, for example by charge pumps.
At the end of the precharge phase, the potential at the nodes MAT and REF evolves dynamically. In particular, assuming that the two loads LDa and LDb are substantially equal (balanced loads), the evolution in time of the potential at the node MAT with respect to the node REF depends on whether the current I,m sunk by the matrix memory cell MC,m (whose value depends on the datum stored in the memory cell itself) is higher or lower than the reference current I,r (a similar reasoning also holds true in the case in which the loads LDa and LDb are not identical, i.e., they form unbalanced loads; in that case, the evolution in time of the potential at the node MAT with respect to the node REF depends on whether the current I,m is higher or lower than a predetermined fraction of the reference current I,r).
The potentials at the nodes MAT and REF are compared to each other by the differential amplifier 125, which amplifies an even slight potential difference to a full-swing logic signal.
The reference current I,r and the loads LDa and LDb are chosen in such a way that the potential at the node REF falls midway between the potential at the node MAT in the different possible programming states of the matrix memory cell (corresponding to different values of the matrix memory cell current I,m). Referring to FIG. 2A, the diagram shows the relationship between the values of the matrix memory cell current I,m and the reference current I,r, in the simple case of a bi-level memory. A horizontal axis I represents possible values of currents of the matrix memory cells and the reference currents. I,m“1” and I,m“0” are the average values of two statistical distributions of memory cell currents in the programming state “1” (usually corresponding to a lower threshold voltage Vth“1”) and “0” (usually corresponding to a higher threshold voltage Vth“0”). A reference current I,r intermediate between the two statistical distributions of currents ensures that the potential difference between the nodes MAT and REF is relatively large in either one of the two programming states (“1” or “0”) of the memory cell to be sensed, and this increases the noise margin and the switching speed of the differential amplifier 125.
However, the separation between the potentials at the nodes MAT and REF of the sense amplifier finds a limit in the value of the supply voltage VDD. In principle, the voltage at the nodes MAT and REF may in fact swing from ground to the supply voltage VDD; from a practical viewpoint, however, the real voltage swing is lower. Due to the presence of the bit line voltage regulators 130a and 130b, the swing is limited to the range going from approximately 1V (the switching threshold of the inverter IN1a and IN1b) to the supply voltage VDD. Assuming that the memory IC supply voltage VDD is in the range from 2.7V to 3.6V, the worst-case maximum separation of the potentials at the nodes MAT and REF may be as low as 1.7V.
The situation is more critical in the case of multi-level memories. Referring to FIG. 2B, the diagram shows the relationship between the memory cell currents and the reference currents in the case of a four-level memory (a memory having memory cells capable of storing two bits). Im“11”, Im“10”, Im“01” and Im“00”, represent the average values of statistical distributions of possible matrix memory cell currents values of current sunk by memory cells in each one of the four possible programming states, corresponding to the logic values “11”, “10”, “01” and “00”, respectively. Given a same biasing condition, the matrix memory cell programmed to the logic value “11” presents a low threshold voltage, and then it sinks a high current Im“11”; the current sunk by the memory cells decreases with the increase of their threshold voltage, until the current becomes very small (possibly zero) when the memory cell is programmed to the logic value “00”. Ir1, Ir2 and Ir3 are values of reference currents used for discriminating the four possible programming states of the four-level memory cells. Each pair of adjacent logic values is discriminated by using the suitable reference current Ir1 (i=1,2,3); for example, the memory cell is considered to be programmed to the level “10” when its current is comprised between the reference current Ir2 and the reference current Ir1. For reading each selected memory cell, a parallel sense amplifier compares simultaneously the matrix memory cell current I,m with the three reference currents Ir1–Ir3.
Assuming as before that the supply voltage VDD is in the range from 2.7V to 3.6V, so that the worst-case maximum separation of the potentials at the nodes MAT and REF may be as low as 1.7V, this means that in this quite narrow voltage range seven different voltages need to be accommodated, corresponding to the seven different currents Im“11”, Im“10”, Im“01” and Im“00” and Ir1, Ir2 and Ir3. Thus, the separation between converted voltages at the nodes MAT and REF may be as low as 1.7V/6=283 mV; even worse, the real, statistical distribution of the currents, as depicted in FIG. 2B, further reduces the above voltage separation, leading to actual values as low as 50 mV.
Such low voltage differences cause the differential amplifier 125 to be slow in switching its output to either one or the other logic state, and to be very sensitive to noise.
The voltage difference between the nodes MAT and REF may be even lower in a case in which the supply voltage is reduced (supply voltages as low as 1.8V are becoming popular), and/or in the case of multi-level memories storing more than two bits per memory cell.
We have also observed that the presence of the loads LDa and LDb is not particularly advantageous, due to reasons of semiconductor chip area; in fact, the number of sense amplifiers needed in a semiconductor memory IC may be relatively high, and it would be desirable to keep the number of devices as low as possible.
Another known sensing circuit structure 300 is depicted in FIG. 3, in which elements identical or corresponding to those of FIG. 1 are identified by the same reference numerals. Different from the previously described structure, in this structure the bit line voltage regulators 130a and 130b are each connected in series to an input branch of a respective current mirror, which is comprised of a P-channel MOSFET P21a and P21b in diode configuration, and which mirrors the current I,m and I,r into a mirror branch of the current mirror, which is comprised of a P-channel MOSFET P22a and P22b, to which the load LDa and LDb is connected. The nodes MAT and REF, which are connected to the inputs of the differential amplifier 125, are represented by the drain electrode of the P-channel MOSFETs P22a and P22b, respectively, in the mirror branches.
The sense amplifier of FIG. 3, similarly to that of FIG. 1, is also affected by problems of limited voltage swing at the nodes MAT and REF. Since the current mirrors P21a and P22a and P21b and P22b work properly only if the P-channel MOSFETs P22a and P22b remain saturated, the swing of the voltage at the nodes MAT and REF is at best in the range from the ground voltage and the supply voltage VDD less the threshold voltage of the P-channel MOSFETs, which is approximately equal to 1V.
From the viewpoint of semiconductor chip area, we observed that the structure of FIG. 3 is instead worse than that of FIG. 1, because the four MOSFETs forming the two current mirrors need to be integrated in addition to the loads LDa and LDb.